The present invention relates generally to integrated circuits, and more particularly, to a flip-flop that retains data during scan testing.
Integrated circuits (ICs) such as microprocessors, microcontroller units (MCUs), systems-on-chips (SOCs), and application specific integrated circuits (ASICs) are widely used in various applications including industrial applications, automobiles, home appliances, and handheld devices. These ICs include circuit modules, such as hard and soft IP cores, digital circuits including latches, registers and combinational logic circuits. ICs often include a self-testing mechanism, referred to as logic built-in-self-test (LBIST), to enable self-checking of logic within the IC. For example, BIST procedures are often integrated in ISO 26262 standard compliant automotive electric and electronic devices where testing of safety features is crucial.
Transition fault testing is performed during BIST to identify and locate signal transition faults in the IC. The test, also known as an at-speed test, is carried out at rated clock speed to test the response of an IC. At-speed tests can be performed as scan tests that involve selecting a scan path (chain of flip-flops) in the IC for testing. An input test pattern of logic zero and one values is provided to a first-flop of the chain and a corresponding output pattern is obtained at the output of last flip-flop of the chain. Subsequently, the output pattern is compared with an expected output pattern to identify faults in the chain.
When LBIST is initiated on a selected circuit, the normal operation of the flip-flops of the circuit is halted and scan testing is performed. Upon completion of LBIST, each flip-flop is reset before resuming normal operation. Due to the sequence of operation, the values stored in each flip-flop (hereinafter referred to as original state) before scan testing are lost. Hence, upon completion of LBIST, each flip-flop of the chain resumes its normal operation from reset; no correlation is maintained with the original state. It is time consuming to return each flip-flop to its original state (rather than the reset state). This may not be desirable, especially for ICs that perform safety critical operations.
Therefore, it would be advantageous to have a flip-flop that retains the state before scan testing, that reduces the time required by the flip-flop to reach its original state after the completion of scan testing, and that generally overcomes the above-mentioned limitations in existing integrated circuits.